1. Field of the Invention
The present invention relates to methods and apparatus for transmitting or conducting electrical signals from a conductive portion of a component, such as a lead or a wire, to an inner layer of a multi-layer substrate or board and, in particular, relates to the performing of such signal transmission or conduction without the use of vias, plated-through-holes, and the like. The present invention also relates to methods for manufacturing multi-layer substrates which are suitable for carrying out the aforementioned functions.
2. Description of the Related Art
Various methods are known for mounting semiconductor packages, resistors, capacitors, inductors, connectors, and other electrical or electronic components on an interface surface such as a printed circuit board (PCB). Two of the more common methods are the plated-through-hole (PTH) method and the surface-mount-technology (SMT) method.
In the PTH method, illustrated in FIG. 1, component mounting is accomplished by inserting a lead 101 of a component 102 through a PTH 103 formed in a PCB 104 and then soldering the lead to form a solder joint 105 fastening the lead in contact with the PTH. The PTH method is applicable for use in connection with both single-layer and multi-layer PCBs.
In the SMT method, illustrated in FIGS. 2(a)-2(d), each lead 101 of a component 102, rather than being soldered to extend through a PTH in a PCB, is soldered onto a conductive portion of a top surface of the PCB 104 known as a pad. If the component is a leadless chip carrier, as shown in FIG. 2(d), a conductive section of the component 102 is soldered onto the pad. A solder joint 105 then maintains each lead 101 of the leaded chip carriers, FIGS. 2(a)-2(c), or each conductive section of the leadless chip carrier, FIG. 2(d), in a fastened relationship with respect to the PCB 104. In accordance with the SMT method, each lead 101 of the leaded chip carriers can have a "Gullwing" configuration, as in FIG. 2(a); a "J-Lead" configuration, as in FIG. 2(b); or a "Butt Lead" configuration, as in FIG. 2(c).
An example of a conventional multi-layer PCB 104, with the individual layers of the PCB shown separated for ease of explanation, is shown in FIG. 3. In the example of FIG. 3, the lead 101a is a PTH lead of a component (not shown) which extends through a PTH 103 formed in the PCB 104 and which is soldered to form a solder joint 105 fastening the lead within the PTH. The PTH 103 extends through all of the layers of the PCB 104. In the example of FIG. 3, the lead 101b is an SMT lead of a component (not shown) mounted to a bonding pad 106 formed on the upper surface of the PCB 104.
Vias are used to interconnect layers of a multi-layer PCB. A via is a conventional component that is similar to the aforementioned PTH, except that a via is not typically large enough to accommodate receipt of a lead or the like therein. A via may extend through the layers of a multi-layer PCB to allow the transmission of signals between such layers.
Three types of conventional vias for a multi-layer PCB 104 are shown in FIG. 4. In FIG. 4, via 107a is a via extending through all of the layers of the PCB 104. Via 107b is a blind via extending from either the top or bottom of the PCB 104 through some, but not all, of the layers of the PCB. Only the side portions of a conventional blind via are plated with conductive material; the bottom portion is filled with insulative pre-preg or epoxy resin material rather than being plated. Via 107c is a buried via extending through only internal layers of the PCB 104; it does not extend all the way to the top or the bottom of the PCB.
The vias of FIG. 4 may be formed by a process wherein holes are drilled in each of the layers, the holes are plated, and then the layers are laminated together. Blind vias result when the layers are laminated such that a drilled portion of one layer abuts, at only one side thereof, an undrilled portion of another one of the layers. Buried vias result when the layers are laminated such that a drilled portion of one layer abuts, at both sides thereof, undrilled portions of other ones of the layers, respectively. The manufacturing process performed to achieve a PCB such as that shown in FIG. 4 is very expensive.
FIG. 5 is a side view of a multi-layer PCB 104. In FIG. 5, a lead 101 of a component (not shown) extends through a PTH 103 formed in the PCB and is soldered to form a solder joint (not shown) fastening the lead within the PTH. The PTH 103 extends through all of the layers of the PCB shown in FIG. 5. Also, in FIG. 5, a plated via 107 extends through all of the layers of the PCB 104. Conductive traces 108a, 108b, 108c, and 108d are formed on various layers of the PCB 104, respectively, and a number of the traces (for example, traces 108a and 108d) provide an electrically conductive path between the via 107 and the PTH 103. By virtue of the via 107, the PTH 103, and the various traces, an electrical signal may be transmitted, for example, between the PTH lead 101, the trace 108a formed on the top surface of the PCB 104, and one or more inner layers of the PCB.
FIG. 6 is a partial side view of a multi-layer PCB 104 incorporating an SMT pad 106, a plated via 107, and traces 108a, 108b, 108c, and 108d formed at various levels thereof, respectively. In FIG. 6, an SMT lead 101 of a component (not shown) is mounted to the bonding pad 106 formed on the top surface of the PCB. A conductive trace 108a formed on the upper surface of the PCB connects the bonding pad 106 and the via 107, allowing electrical signals to be transmitted between the SMT lead 101 and traces at various other levels of the PCB. As an example, the configuration illustrated in FIG. 6 allows the transmission of electrical signals between the SMT lead 101 and the trace 108d formed on the bottom surface of the PCB 104. It is important to note that for every SMT lead which connects to an inner layer of the PCB 104, there must be a trace and a via. Consequently, large amounts of area are sacrificed at the various levels of the PCB.
FIG. 7 is a partial perspective view of a conventional multi-layer PCB 104 with the individual layers of the board shown separated for ease of explanation. Like the PCB illustrated in FIG. 6, the PCB of FIG. 7 incorporates an SMT bonding pad 106, a plated via 107, and traces 108a and 108b formed at various levels thereof, respectively. In FIG. 7, an SMT lead 101 of a component (not shown) is mounted to the bonding pad 106.
Every conventional PCB known to the inventors makes inefficient use of its surface and inner layers. Current commercial production technology allows for 80 traces per linear inch of the PCB, based on 0.006 inch wide traces and requisite clearances. As the density of semiconductor packages and the like increases, it becomes more difficult for designers to efficiently convey signals between surfaces and inner layers of the PCB. Signals are currently brought to such inner layers by using traces which run to vias and thus are connected to the inner layers. These vias and related traces occupy a significant amount of area, reducing density and complicating signal routing. The problem is compounded when using advanced components having a large number of contacts per linear or square inch.
High-density interconnect technology is currently attempted by reducing the size of traces, PTHs, vias, and line spacing. In attempting to achieve high-density, the prior art contemplates the manufacture of PCBs with thinner traces placed closer together. Such attempts at high-density, however, may reduce manufacturing yields and increase costs due to the extreme tolerances that are necessary.
Conventional vias, while allowing the transmission of signals between various PCB layers, pose a number of electrical and mechanical problems. For example, large numbers of conventional vias add unwanted capacitance to the signal, power, and ground planes. Moreover, vias increase the number of drill operations required to manufacture a multi-layer PCB and, therefore, increase cost and reduce yield. The term "drill operation" is used herein to describe the number of vias times the number of board layers. Also, vias reduce the amount of available signal routing paths, and reduce the amount of PCB surface area available for the placement or mounting of component leads.
Routeability is especially affected in an adverse manner by the use of vias in connection with multi-layer PCBs. This is particularly true as the number of layers in a PCB increases. As an example, for each PCB layer through which a via extends, in addition to the space required for the via itself, space is also necessary for the traces required to connect the via to other conductive elements at each level. Moreover, each via must be of an increased size due to the conductive plating which the via requires to ensure that the via is capable of conducting electrical signals. Trace clearance between other components, pads, and other traces further reduces density.
As is evident from the foregoing, even though conventional PCBs may carry conductive elements at a number of levels, limitations on the acceptable spacing of traces, lines and, in particular, PTHs and plated vias, limit the density of the conductivity of conventional PCBs. Consequently, conventional PCBs are not sufficient to meet the needs of existing and/or future semiconductor and computer technology.
Existing PCB and other interface technology has already failed to keep pace with current semiconductor and computer technology, and as computer and microprocessor speeds continue to climb, with space efficiency and routeability becoming increasingly important, multi-layer substrates having more efficient interconnect characteristics will be required. The PCBs discussed above fall short of current and contemplated semiconductor-related and computer-related requirements.